The present invention relates, in general, to etch processes and, more particularly, to a sloped contact etch process and a controlled isotropy reactive ion etcher.
Semiconductor integrated circuits comprise a plurality of circuits and devices which are interconnected by one or more patterned metal layers, also called interconnect layers, formed on a top surface of the integrated circuit. The interconnect layers are separated from each other and the circuit by interlayer dielectric films. As device dimensions approach a sub-micron level, one limiting factor for further reduction in size is area required for device interconnections. A major component of interconnect area is size of contact windows and vias, which are etched in the interlayer dielectric. Contact windows are etched to expose portions of the underlying circuit or lower interconnect layer. An upper interconnect layer is formed on top of the interlayer dielectric and in contact with the underlying circuit or the lower interconnect layer through the contact window.
Etch processes are classified generally as isotropic or anisotropic. In either process, windows formed in a patterned masking layer define geometry of the contact window. Isotropic etch processes undercut the masking layer while vertically etching the dielectric layer. Anisotropic etch processes create vertical sidewalls with the top and bottom of the contact window having substantially the same dimensions as the windows formed in the masking layer. Isotropic etch processes are undesirable for sub-micron geometries because the undercut significantly increases lateral area required for the contact window. Although anisotropic etch processes are compatible with the sub-micron dimensions of contact windows, the vertical sidewalls results in a via which is difficult to fill when the upper interconnect layer is deposited.
Sloped contact etch processes using alternating steps of anisotropic etching and isotropic mask erosion are described in U.S. Pat. Nos. 4,902,377 and 4,698,128 issued to some of the inventors of the present invention and assigned to the same assignee as the present invention, and incorporated herein by reference. The isotropic mask erosion step increases size of the upper portion of the via while maintaining the original printed contact dimension at the lower portion of the via. It is highly desirable to perform such a multi-step etch process in a single piece of equipment to reduce handling and contamination.
A multi-step sloped contact etch process relies heavily on an ability to isotropically etch a masking layer in a reactive ion etcher. Reactive ion etchers are optimized, however, for anisotropic etching. In particular, hexode reactive ion etchers, such as an AME 8110 built by Applied Materials Corporation, have substantial asymmetry between cathode and anode surface areas which results in a high degree of anisotropy and limited ability to perform an isotropic etch. Also, reactive ion etchers develop a self-generated DC bias on the cathode which accelerates positive ions in the plasma towards substrates mounted on the cathode, further increasing anisotropy.
Limited isotropy in the multi-step sloped contact etch process results in excessive vertical photoresist erosion during the mask erosion step. Vertical photoresist erosion is combated by thicker photoresist masks and correspondingly larger printed contact geometries. If thinner resist is used to achieve small contact geometries, control over the slope of the via is reduced. What is needed is a reactive ion etcher which can be easily switched between isotropic etching and anisotropic etching modes.